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CY2071A
Single-PLL General-Purpose EPROM Programmable Clock Generator
Features
* Single phase-locked loop architecture * EPROM programmability * Factory-programmable (CY2071A, CY2071AI) or field-programmable (CY2071AF, CY2071AFI) device options * Up to three configurable outputs * Low skew, low jitter, high-accuracy outputs * Internal loop filter * Power management (OE) * Frequency select options * Configurable 5V or 3.3V operation * 8-pin 150-mil SOIC package
Benefits
* * * * * * * * * * Generates a custom frequency from an external source Easy customization and fast turnaround Programming support available for all opportunities Generates three related frequencies from a single device Meets critical industry standard timing requirements Alleviates the need for external components Supports low-power applications Three outputs with two user-selectable frequencies Supports industry standard design platforms Industry standard packaging saves on board space
Selector Guide
Part Number CY2071A CY2071AI CY2071AF CY2071AFI Outputs 3 3 3 3 Input Frequency Range 10 MHz-25 MHz (external crystal) 1 MHz-30 MHz (reference clock) 10 MHz-25 MHz (external crystal) 1 MHz-30 MHz (reference clock) 10 MHz-25 MHz (external crystal) 1 MHz-30 MHz (reference clock) 10 MHz-25 MHz (external crystal) 1 MHz-30 MHz (reference clock) Output Frequency Range 500 kHz-130 MHz (5V) 500 kHz-100 MHz (3.3V) 500 kHz-100 MHz (5V) 500 kHz-80 MHz (3.3V) 500 kHz-100 MHz (5V) 500 kHz-80 MHz (3.3V) 500 kHz-90 MHz (5V) 500 kHz-66.6 MHz (3.3V) Specifics Factory Programmable Commercial Temperature Factory Programmable Industrial Temperature Field Programmable Commercial Temperature Field Programmable Industrial Temperature
Logic Block Diagram for CY2071A
XTALIN XTALOUT PLL Block REFERENCE OSCILLATOR CLKA EPROMConfigurable Multiplexer and Divide Logic
CLKB
CLKC
OE / FS
Pin Configuration
8-pin SOIC Top View
CLKA GND XTALIN XTALOUT 1 2 3 4 8 7 6 5 OE/FS VDD CLKC CLKB
Cypress Semiconductor Corporation Document #: 38-07139 Rev. *D
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised August 3, 2006
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CY2071A
Pin Summary
Name CLKA GND XTALIN CLKB CLKC VDD OE / FS
[1] [1, 2]
Number 1 2 3 4 5 6 7 8 Configurable Clock Output Ground
Description
Reference Crystal Input or External Reference Clock Input Reference Crystal Feedback Configurable Clock Output Configurable Clock Output Voltage Supply Output Control Pin, either Output Enable or Frequency Select Input (Active HIGH, internal pull-up resistor to VDD)
XTALOUT
Functional Description
The CY2071A is a general-purpose clock synthesizer designed for use in applications such as modems, disk drives, CD-ROM drives, video CD players, games, set-top boxes, and data/telecommunications. The device offers up to three configurable clock outputs in an 8-pin, 150-mil SOIC package and can operate off either a 3.3V or 5V power supply. The on-chip reference oscillator is designed for 10 MHz to 25 MHz crystals. Alternatively, an external reference clock of frequency between 1 MHz and 30 MHz can be used. The CY2071A has one PLL and outputs three factory-EPROM configurable clocks: CLKA, CLKB, and CLKC. The output clocks can originate either from the PLL or the reference, or selected dividers thereof. Additionally, pin 8 can be configured to be an Output Enable or a Select input. The CY2071A can replace multiple Metal Can Oscillators (MCO) in a synchronous system, providing cost and board space savings to the manufacturer. Hence, these devices are ideally suited for applications that require multiple, accurate, and stable clocks synthesized from low-cost generators in small packages. A hard-disk drive is an example of such an application. In this case, CLKA drives the PLL in the Read Controller, while CLKB and CLKC drive the MCU and associated sequencers.
CyClocks Software
CyClocksTM is an easy-to-use software application that allows you to configure any one of the EPROM-Programmable Clocks offered by Cypress. You may specify the input frequency, PLL and output frequencies, and different functional options. Note the output frequency ranges in this data sheet when specifying them in CyClocks to ensure that you stay within the limits. You can download a copy of CyClocks free on the Cypress Semiconductor Corporation web site at www.cypress.com. Use the CY2081 for applications that require unrelated output frequencies. Use the CY2291, CY2292, or CY2907 for applications that require more than three output clocks.
Cypress FTG Programmer
The Cypress Frequency Timing Generator (FTG) Programmer is a portable programmer designed to custom program our family of EPROM Field Programmable Clock Devices. The FTG programmers connect to a PC serial port and allow users of CyClocks software to easily program any of the CY2291F, CY2292F, CY2071AF, and CY2907F devices. The ordering code for the Cypress FTG Programmer is CY3670.
Absolute Maximum Conditions[3, 4]
Parameter VDD VIN TS TA TJ ESDHBM Description Analog Supply Voltage DC Input Voltage Temperature, Storage Temperature, Maximum Soldering (10 sec) Temperature, Junction ESD Protection (Human Body Model) Non-functional Functional Functional MIL-STD-883, Method 3015 Condition Min. -0.5 -0.5 -65 - - 2000 Max. 7.0 150 260 150 - Unit V C C C V
VDD + 0.5 VDC
Notes 1. For best accuracy, use a parallel-resonant crystal, CL = 17 pF. 2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to an external crystal). 3. Stresses greater than those listed in this table may cause permanent damage to the device. 4. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Document #: 38-07139 Rev. *D
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CY2071A
Operating Conditions[5]
Parameter VDD VDD TA CL fREF tPU Supply Voltage, 5.0V Operation Supply Voltage, 3.3V Operation Commercial Operating Temperature, Ambient Industrial Operating Temperature, Ambient Max. Load Capacitance per Output (5V Operation) Max. Load Capacitance per Output (3.3V Operation) External Reference Crystal External Reference Clock[6, 7] Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Description Min. 4.5 3.0 0 -40 - - 10.0 1.0 0.05 Max. 5.5 3.6 70 85 25 15 25.0 30.0 50 Unit V V C C pF pF MHz MHz ms
Electrical Characteristics, Commercial 5.0V: VDD = 5V 10%, TA = 0C to +70C[8]
Parameter VOH VOL VIH VIL IIH IIL IOZ IDD Description HIGH-Level Output Voltage LOW-Level Output Voltage HIGH-Level Input Voltage[9] LOW-Level Output Input LOW Current Output Leakage Current VDD Supply Current[10] Voltage[9] Input HIGH Current IOH = -4.0 mA IOL = 4.0 mA Except Crystal Pins Except Crystal Pins VIN = VDD - 0.5V VIN = 0.5V Three State Outputs VDD = VDD max. 5V operation, CL = 25 pF Conditions Min. 2.4 - 2.0 - - - - Typ. - - - - - - - 40 Max. - 0.4 - 0.8 10 150 250 60 Unit V V V V A A A mA
Electrical Characteristics, Commercial 3.3V: VDD = 3.3V 10%, TA = 0C to 70C[8]
Parameter VOH VOL VIH VIL IIH IIL IOZ IDD Description HIGH-Level Output Voltage LOW-Level Output Voltage HIGH-Level Input Voltage[9] LOW-Level Output Voltage[9] Input HIGH Current Input LOW Current Output Leakage Current VDD Supply Current[10] IOH = -4.0 mA IOL = 4.0 mA Except Crystal Pins Except Crystal Pins VIN = VDD - 0.5V VIN = 0.5V Three State Outputs VDD = VDD max. 3.3V operation, CL = 15 pF Conditions Min. 2.4 - 2.0 - - - - - Typ. - - - - - - - 24 Max. - 0.4 - 0.8 10 150 250 40 Unit V V V V A A A mA
Notes: 5. Electrical parameters are guaranteed with these operating conditions. Values for 3.3V operation are shown in parentheses. 6. External input reference clock must have a duty cycle between 40% and 60%, measured at VDD/2. 7. Please refer to application note "Crystal Oscillator Topics" for information on AC-coupling the external input reference clock. 8. See "CY2071A and CY2907 Clock Generators" Application Note for important customer clarification. 9. Xtal inputs have CMOS thresholds. 10. Load = max, typical configuration, fREF = 14.318 MHz. Specific configurations may vary. A close approximation of IDD can be derived by the following formula: IDD(mA) = VDD*(6.25+(0.055*FREF) + (0.0017*CLOAD*(FCLKA+FCLKB+FCLKC))). CLOAD is specified in pF and F is specified in MHz.
Document #: 38-07139 Rev. *D
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CY2071A
Electrical Characteristics, Industrial 5.0V: VDD = 5.0V 10%, TA = -40C to 85C[8]
Parameter VOH VOL VIH VIL IIH IIL IOZ IDD Description HIGH-Level Output Voltage LOW-Level Output Voltage HIGH-Level Input Voltage[9] LOW-Level Output Voltage[9] Input HIGH Current Input LOW Current Output Leakage Current VDD Supply Current[10] IOH = -4.0 mA IOL = 4.0 mA Except Crystal Pins Except Crystal Pins VIN = VDD - 0.5V VIN = 0.5V Three State Outputs VDD = VDD max. 5V operation, CL = 25 pF 40 2.0 0.8 10 150 250 75 Conditions Min. 2.4 0.4 Typ. Max. Unit V V V V A A A mA
Electrical Characteristics, Industrial 3.3V VDD =3.3V 10%, TA = -40C to +85C[8]
Parameter VOH VOL VIH VIL IIH IIL IOZ IDD Description HIGH-Level Output Voltage LOW-Level Output Voltage HIGH-Level Input Voltage[9] LOW-Level Output Voltage[9] Input HIGH Current Input LOW Current Output Leakage Current VDD Supply Current[10] IOH = -4.0 mA IOL = 4.0 mA Except Crystal Pins Except Crystal Pins VIN = VDD - 0.5V VIN = 0.5V Three State Outputs VDD = VDD max. 3.3V operation, CL = 15 pF 24 2.0 0.8 10 150 250 50 Conditions Min. 2.4 0.4 Typ. Max. Unit V V V V A A A mA
Switching Characteristics, Commercial 5.0V[11]
Parameter t1 Name Output Period Description Clock output range 5V operation 25-pF load CY2071A CY2071AF t1A t1B t1C Clock Jitter Clock Jitter Clock Jitter[12] Output Duty Cycle Peak-to-peak period jitter (t1 max. - t1 min.), % of clock period, fOUT 16 MHz Peak-to-peak period jitter (16 MHz fOUT 50 MHz) Peak-to-peak period jitter (fOUT > 50 MHz) Duty cycle[13, 14] for outputs, (t2 / t1) fOUT 60 MHz 45% 40% Min. 7.692 [130 MHz] 10 [100 MHz] 0.8 350 250 50% 50% 1.5 1.5 Typ. Max. 2000 [500 kHz] 2000 [500 kHz] 1 500 350 55% 60% 2.5 2.5 0.5 ns ns ns Unit ns ns % ps ps
Output Duty Cycle[12] Duty cycle[14] for outputs, (t2 / t1), fOUT > 60 MHz t3 t4 t5 Rise Time[12] Fall Time Skew
[12]
Output clock rise time Output clock fall time Skew delay between any two outputs with identical frequencies (generated by the PLL)
Notes: 11. Guaranteed by design, not 100% tested. 12. When the output clock frequency is between 100 MHz and 130 MHz at 5V, the maximum capacitive load for these measurements is 15 pF. 13. Reference Output duty cycle depends on XTALIN duty cycle. 14. Measured at 1.4V.
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CY2071A
Switching Characteristics, Commercial 3.3V[11]
Parameter t1 Name Output Period Description Clock output range 3.3V operation CY2071AS 15-pF load CY2071AF Peak-to-peak period jitter (t1 max. - t1 min.), % of clock period, fOUT 16 MHz Peak-to-peak period jitter (16 MHz fOUT 50 MHz) Peak-to-peak period jitter (fOUT > 50 MHz) Duty cycle[13, 14] for outputs, (t2 / t1) fOUT 60 MHz Duty cycle[14] for outputs, (t2 / t1), fOUT > 60 MHz Output clock rise time Output clock fall time Skew delay between any two outputs with identical frequencies (generated by the PLL) 45% 40% Min.
10 [100 MHz] 12.50 [80 MHz]
Typ.
Max.
2000 [500 kHz] 2000 [500 kHz]
Unit ns ns % ps ps
t1A t1B t1C
Clock Jitter Clock Jitter Clock Jitter[12] Output Duty Cycle Output Duty Cycle[12]
0.8 350 250 50% 50% 1.5 1.5
1 500 350 55% 60% 2.5 2.5 0.5
t3 t4 t5
Rise Time[12] Fall Time[12] Skew
ns ns ns
Switching Characteristics, Industrial 5.0V[11]
Parameter t1 Name Output Period Description Clock output range 5.0V operation CY2071AI 25-pF load CY2071AFI t1A Clock Jitter Peak-to-peak period jitter (t1 max. - t1 min.), % of clock period, fOUT 16 MHz Peak-to-peak period jitter (16 MHz fOUT 50 MHz) Peak-to-peak period jitter (fOUT > 50 MHz) Duty cycle[13, 14] for outputs, (t2 / t1) fOUT 60 MHz Duty cycle[14] for outputs, (t2 / t1), fOUT > 60 MHz Output clock rise time Output clock fall time Skew delay between any two outputs with identical frequencies (generated by the PLL) 45% 40% Min. 10 [100 MHz] 11.1 [90 MHz] 0.8 Typ. Max. 2000 [500 kHz] 2000 [500 kHz] 1 Unit ns ns %
t1B t1C
Clock Jitter Clock Jitter[12] Output Duty Cycle Output Duty Cycle[12]
350 250 50% 50% 1.5 1.5
500 350 55% 60% 2.5 2.5 0.5
ps ps
t3 t4 t5
Rise time[12] Fall time[12] Skew
ns ns ns
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CY2071A
Switching Characteristics, Industrial 3.3V[11]
Parameter t1 Name Output Period Description Clock output range 3.3V operation CY2071AI 15-pF load CY2071AFI t1A t1B t1C Clock Jitter Clock Jitter Clock Jitter[12] Output Duty Cycle Output Duty Cycle[12] t3 t4 t5 Rise time[12] Fall time[12] Skew Peak-to-peak period jitter (t1 max. - t1 min.), % of clock period, fOUT 16 MHz Peak-to-peak period jitter (16 MHz fOUT 50 MHz) Peak-to-peak period jitter (fOUT > 50 MHz) Duty cycle[13, 14] for outputs, (t2 / t1) fOUT 60 MHz Duty cycle[14] for outputs, (t2 / t1), fOUT > 60 MHz Output clock rise time Output clock fall time Skew delay between any two outputs with identical frequencies (generated by the PLL) 45% 40% Min. 12.50 [80 MHz] 15.0 [66.6 MHz] 0.8 350 250 50% 50% 1.5 1.5 Typ. Max. 2000 [500 kHz] 2000 [500 kHz] 1 500 350 55% 60% 2.5 2.5 0.5 ns ns ns Unit ns ns % ps ps
Switching Waveforms
Figure 1. All Outputs Duty Cycle and Rise/Fall Time
t1 t2 OUTPUT 2.4V 0.4V t3 2.4V 0.4V t4 VDD 0V
Figure 2. Output-Output Clock Skew
OUTPUT OUTPUT t5
Test Circuit
VDD 0.1 F OUTPUTS 2 CLK output CLOAD 7
GND Document #: 38-07139 Rev. *D Page 6 of 9
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CY2071A
Ordering Information
Ordering Code CY2071ASC-XXX CY2071ASC-XXXT CY2071ASL-XXX CY2071ASL-XXXT CY2071ASI-XXX CY2071ASI-XXXT CY2071AF CY2071AFT CY2071AFI CY2071AFIT CY3670 Lead-Free CY2071ASXC-XXX CY2071ASXC-XXXT CY2071ASXL-XXX CY2071ASXL-XXXT CY2071ASXI-XXX CY2071ASXI-XXXT CY2071AFXC CY2071AFXCT CY2071AFXI CY2071AFXIT 8-Pin (150-Mil) SOIC 8-Pin (150-Mil) SOIC - Tape and Reel 8-Pin (150-Mil) SOIC 8-Pin (150-Mil) SOIC- Tape and Reel 8-Pin (150-Mil) SOIC 8-Pin (150-Mil) SOIC- Tape and Reel 8-Pin (150-Mil) SOIC 8-Pin (150-Mil) SOIC- Tape and Reel 8-Pin (150-Mil) SOIC 8-Pin (150-Mil) SOIC- Tape and Reel 5.0V, Commercial, Factory Programmable 5.0V, Commercial, Factory Programmable 3.3V, Commercial, Factory Programmable 3.3V, Commercial, Factory Programmable 5V/3.3V, Industrial, Factory Programmable 5V/3.3V, Industrial, Factory Programmable 5V/3.3V, Commercial, Field Programmable 5V/3.3V, Commercial, Field Programmable 5V/3.3V, Industrial, Field Programmable 5V/3.3V, Industrial, Field Programmable Package Type 8-Pin (150-Mil) SOIC 8-Pin (150-Mil) SOIC - Tape and Reel 8-Pin (150-Mil) SOIC 8-Pin (150-Mil) SOIC - Tape and Reel 8-Pin (150-Mil) SOIC 8-Pin (150-Mil) SOIC - Tape and Reel 8-Pin (150-Mil) SOIC 8-Pin (150-Mil) SOIC - Tape and Reel 8-Pin (150-Mil) SOIC 8-Pin (150-Mil) SOIC - Tape and Reel FTG Programmer Operating Range 5.0V, Commercial, Factory Programmable 5.0V, Commercial, Factory Programmable 3.3V, Commercial, Factory Programmable 3.3V, Commercial, Factory Programmable 5V/3.3V, Industrial, Factory Programmable 5V/3.3V, Industrial, Factory Programmable 5V/3.3V, Commercial, Field Programmable 5V/3.3V, Commercial, Field Programmable 5V/3.3V, Industrial, Field Programmable 5V/3.3V, Industrial, Field Programmable Custom programming for Field Programmable Clocks
Package Characteristics
Package 8 Pin SOIC JA (C/W) 170 JC (C/W) 35 Transistor Count 5436
Document #: 38-07139 Rev. *D
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CY2071A
Package Drawing and Dimensions
Figure 3. 8-lead (150-Mil) SOIC S8
8 Lead (150 Mil) SOIC - S08
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3. REFERENCE JEDEC MS-012
0.230[5.842] 0.244[6.197]
0.150[3.810] 0.157[3.987]
4. PACKAGE WEIGHT 0.07gms
PART # S08.15 STANDARD PKG. 5 8 SZ08.15 LEAD FREE PKG.
0.189[4.800] 0.196[4.978]
SEATING PLANE
0.010[0.254] 0.016[0.406]
X 45
0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0~8 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249]
0.0138[0.350] 0.0192[0.487]
51-85066-*C
CyClocks is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY2071A
Document History Page
Document Title: CY2071A Single-PLL General-Purpose EPROM Programmable Clock Generator Document Number: 38-07139 REV. ** *A *B *C *D ECN NO. Issue Date 110248 121827 279389 296792 492389 12/17/01 12/14/02 See ECN See ECN See ECN Orig. of Change SZV RBI RGL RGL RGL Description of Change Change from Spec number: 38-00521 to 38-07139 Power up requirements added to Operating Conditions Information Added lead-free devices Minor Typo: missed one letter (C) in the ordering code Added a note on all Electrical specs table specifying the Application notes name for customer's clarification Reformatted using new template
Document #: 38-07139 Rev. *D
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